1. Technical Field
The present invention relates to data processing, and, more particularly to data processing systems and methods capable of recalibrating to optimize performance during the course of their functional operations.
2. Description of the Related Art
In high speed data processing systems, chip to chip interfaces (such as Elastic Interfaces) have been provided to compensate for static manufacturing and design variables. Examples of static variables are doping levels in silicon in the chips, variations in electrical line length and width on chips and Printed Circuit Boards (PCB's), inherent design tolerances, and the like. Static variables are typically fixed after manufacturing and rennin generally constant over the life of the product. In order to adjust for the effect of static variables, systems and methods to compensate have been developed. Compensation for these variables occurred at system power-on. During the compensation process, signals on an interface in the system were appropriately adjusted on the receive chip's silicon to optimize performance. This compensation is accomplished in what are known in the art as tunable interfaces. An example tunable interface process from the assignee of the present application is referred to as the Initialization Alignment Procedure (IAP). The IAP is described, for example, in a co-pending commonly owned, U. S. patent application: “Elastic Interface Apparatus and Method Thereof”, Ser. No. 09/434,801, now U.S. Pat No. 6.542.999, filed Nov. 5, 1999. The IAP requires on the order of half a millisecond to accomplish and is a sub-process within the composite high speed data processing system power-on procedure, which typically can take several seconds or minutes to complete.
As microprocessor frequencies continue to increase, their buses to cache, memory, and I/O devices must also increase in frequency to keep the processor fed with instructions and data. To reach these high bus speeds, more aggressive interface device designs must be incorporated on the microprocessor and support chips. Additionally, in an operating computer system, changes in temperature and voltage seen by the chips transmitting and receiving data on the bus interfaces of the system normally occur. These changes may cause the timing of data being transmitted across that bus interface to drift. Past interface designs took this variation into account as part of the margin for uncertainty and resulted in much slower interface speeds since the drift terms accounted for up to 50% of the data valid window margins.